Service Details

Current service offerings are focused on the two engineering categories of Custom IC Implementation and Foundry & Design Support.  

Custom IC Implementation

Services in this category include Standard Cell Layout, Analog Cell Layout, IC Floorplanning & Assembly, IC Place & Route, and Physical Verification.

Standard Cell Layout

Standard cell layout includes physical implementation of individual standard cells as part of your existing library or the physical implementation of an entirely new standard cell library.

Analog Cell Layout

Analog cell layout includes physical implementation of individual analog primitive cells, for example a Comparator, and assembly of analog primitive cells into standalone analog functions, such as a Digital to Analog Converter.

IC Floorplanning and Assembly

IC Floorplanning is the process of developing a plan for assembling the chip.  We plan elements like pad placement, IP block placement, custom analog block placement, power routes, critical routes, and routing channels. The process of chip level floorplanning involves coordinating with package and/or hybrid designers, the IC architect, digital designers, and analog designers. Chip level Floorplanning is often the starting point of the IC layout and will dictate many your constraints and requirements for analog cell layout.

Assembly is the process of completing the manual layout work to make the design ready for physical verification. Analog block assembly is the process of interconnecting individual analog blocks into a larger system of analog blocks. In addition to wiring the connection between the analog blocks this assembly may also include installing a variety of the specialized shields that you specify.

IC Chip level assembly is the process of completing the chip level routing and adding any special structures necessary per the chip level requirements. It also involves adding special structures necessary for IC fabrication, e.g. part numbers and tuning forks.

IC Place & Route

IC Place & Route is the process of using automated Place & Route tools to route either digital blocks, analog blocks, or full chip assembly.

Whenever possible, CDBC recommends full chip assembly using an automated Place & Route tool. Further, we recommend starting the Place & Route process as early as possible to manage the floorplan and test the Place & Route and Physical Verification processes. There are several advantages to doing this. First, the majority of the process can be scripted allowing for expediency and reproducibility in future iterations and revisions. Second, the process promotes a ‘correct by construction’ design methodology that streamlines the entire process to foundry release (tape-out). Third, when changes are made, this process opens the door to continuous regression testing of the Place & Route and the Physical Verification processes.

Physical Verification

Physical Verification is the process of verifying that your physical layout is implemented to the specifications of the schematic or netlist and that the physical layout is compliant with your foundry’s design rules.

Foundry & Design Support

IC Design Flow Management

IC Design Flow Management involves the development and/or maintenance of the front-end through back-end IC design process. CDBC can provide this service for a multi-vendor flow as well as a single vendor flow as there is no conflict of interest between CDBC and the design tool vendors. The following describes activities that may be part of this service. The activities fall into four distinct categories: Process Consulting, Programming, Education, and Testing. The services/activities listed are not comprehensive and will be customized to your particular needs.

Process Consulting

Process consulting contains a series of consulting activities to review your current IC design process, analyze opportunities for improvement, and plan changes to the IC design process with specific goals in mind. Typical enhancement opportunities will involve improving automation, repeatability, and quality.

Programming

Custom programming, generally in the form of scripts, is the glue that holds the design flow together. Programming enables efficiencies, assures repeatability, maintains quality, and guarantees predictability. CDBC has proficiency with compiled programming languages such as C and C++, interpreted languages like TCL and Perl, and tool related languages like Skill and SVRF. Great care is taken to bound the scope of programming applications to your individual needs.

Education

Education is essential for the proper and efficient use of the IC design flow. This activity consists of the generation of documentation. To efficiently roll out new processes or changes formal training can be developed for your team.

Testing

Testing is an important aspect of maintaining an existing IC design flow. There are a number of factors that conspire to breakdown the IC design flow over time. Some of these factors are enhancements, new PDK releases, new design tool revisions, and new product designs that add new constraints. Activities included in this category are Regression Testing and Debug and Design Tool Revision Upgrade.

Offload your team from the maintenance activities necessary to effectively use your foundry’s PDK. PDK Management involves loading new versions of the PDK, testing that the new release works in your design environment, and releasing the PDK to your design team.

Are you looking for a new process as a platform for your next design? CDBC will work with your team to select the best process for your design requirements and business constraints.

Whether you are trying to increase design process throughput or operate the process with fewer hands-on resources; design process automation is essential for maintaining an efficient, repeatable, and predictable quality design process. At CDBC we’ll analyze your design process to determine the optimal application of automation and work with your team to implement the plan.